Tracking Radar Digital Matched-Filter ASIC Design
نویسندگان
چکیده
Matched-filter is widely used in real time signal processing, especially in Radar Signal Processing. This paper provides a novel structure of digital matched-filter used in tracking radar system. This design applies block-floating-point arithmetic to improve the precision. The whole digital matched-filter is implemented in only one chip of FPGA. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signal pulse compression in 102us. Key-Words: matched-filter, parallel processing, low power dissipation, FFT, FPGA
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